PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
These sets of registers report the number of block interleave parity (BIP-2) errors
detected in TU #1 in TUG2 #2 to TUG2 #7 in the previous accumulation interval.
These registers have no effect in TU3 mode. These registers do not saturate.
BIP[10:0]:
The BIP[10:0] bits report the number of tributary path bit-interleaved parity
errors that have been detected since the last time the BIP-2 registers were
polled. The BIP-2 registers are polled by writing to any of the Input Signal
Activity Monitor, Accumulate Trigger register. The write access transfers the
internally accumulated error count to the BIP-2 registers within 10 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation. BIP-2 errors may be accumulated on a nibble basis or block
basis as controlled by the BLKBIP register bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
226
PMC [ PMC-SIERRA, INC ]
