PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
FIGURE 18- STM-1 INPUT BUS TIMING - SIMPLE STS-1/AU3
CASE 390
FIGURE 19- STM-1 INPUT BUS TIMING - COMPLEX STS-1 / AU3
CASE 391
FIGURE 20- STM-1 INPUT BUS TIMING - STS-1 / AU3 (VT/TU
POINTER INTERPRETATION DISABLED) ..................................................392
FIGURE 21- STM-1 INPUT BUS TIMING - AU4 CASE................................393
FIGURE 22- STM-4 INPUT BUS TIMING - STS-1/AU3 CASE.....................394
FIGURE 23- STM-1 OUTPUT BUS TIMING - STS-1 SPES / AU3
VCS CASE 396
FIGURE 24- STM-1 OUTPUT BUS TIMING - AU4 VC CASE......................398
FIGURE 25- STM-4 OUTPUT BUS TIMING - STS-1 SPES / AU3
VCS CASE 399
FIGURE 26- STM-1 (STS-3) INTERFACE, BY-PASSED AND
NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................400
FIGURE 27- STM-4 (STS-12) INTERFACE, BY-PASSED AND
NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................401
FIGURE 28- TRIBUTARY PATH OVERHEAD SERIALIZATION
FUNCTIONAL TIMING..................................................................................404
FIGURE 29- RECEIVE ALARM PORT FUNCTIONAL TIMING....................407
FIGURE 30- MICROPROCESSOR INTERFACE READ ACCESS
TIMING (INTEL MODE)................................................................................413
FIGURE 31- MICROPROCESSOR INTERFACE READ ACCESS
TIMING (MOTOROLA MODE)......................................................................414
FIGURE 32- MICROPROCESSOR INTERFACE WRITE ACCESS
TIMING (INTEL MODE)................................................................................417
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
xix
PMC [ PMC-SIERRA, INC ]
