PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
MONIS bit is set low. Interrupts due to elastic store errors and pointer
justification events are masked when PEE is set low.
ESEI:
The ESEI bit reports and acknowledges the status of elastic store error
interrupts for tributary TU #1 in TUG2 #1 or TU3 depending on whether the
VTPP is in TU3 mode. Interrupts are generated upon FIFO underflows and
overflows. ESEI is set high when an elastic store error occurs and is cleared
immediately following a read of this register, which also acknowledges and
clears the interrupt. ESEI remains valid when interrupts are not enabled (PEE
set low) and may be polled to detect elastic store error events.
PJEI:
The PJEI bit reports and acknowledges the status of the positive pointer
justification event interrupts for tributary TU #1 in TUG2 #1 or TU3 depending
on whether the VTPP is in TU3 mode. When the MONIS bit is set high,
interrupts are generated upon reception of a positive pointer justification event
in the incoming stream. When the MONIS bit is set low, interrupts are
generated upon generation of a positive pointer justification event in the
outgoing stream. PJEI is set high when a positive pointer justification event
occurs in the monitored stream and is cleared immediately following a read of
this register, which also acknowledges and clears the interrupt. PJEI remains
valid when interrupts are not enabled (PEE set low) and may be polled to
detect positive pointer justification events.
NJEI:
The NJEI bit reports and acknowledges the status of the negative pointer
justification event interrupts for tributary TU #1 in TUG2 #1 or TU3 depending
on whether the VTPP is in TU3 mode. When the MONIS bit is set high,
interrupts are generated upon reception of a negative pointer justification
event in the incoming stream. When the MONIS bit is set low, interrupts are
generated upon generation of a negative pointer justification event in the
outgoing stream. NJEI is set high when a negative pointer justification event
occurs in the monitored stream and is cleared immediately following a read of
this register, which also acknowledges and clears the interrupt. NJEI remains
valid when interrupts are not enabled (PEE set low) and may be polled to
detect negative pointer justification events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
186
PMC [ PMC-SIERRA, INC ]
