PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
instructions are supported. The TUPP+622 identification code is 053630CD
hexadecimal.
10.7 Microprocessor Interface
The Microprocessor Interface Block provides the logic required to interface the
normal mode and test mode registers within the TUPP+622 to a generic
microprocessor bus. The normal mode registers are used during normal
operation to configure and monitor the TUPP+622 while the test mode registers
are used to enhance the testability of the TUPP+622. The register set is
accessed as shown in the Register Memory Map table below. Tributary based
normal mode registers in each STM-1 (STS-3) Tributary Processor (STP) are
arranged in order of transmission; TU #1 in TUG2 #1 of STS-1 #1 is the first
tributary transmitted, while TU #4 in TUG2 #7 of STS-1 #3 is the last. Every
register is documented and identified using the register number (REG #). The
corresponding memory map address for every STM-1 (STS-3) Tributary
Processor (STP #1, #2, #3, #4) is given in the table. Register numbers or
addresses that are not shown are not used and must be treated as Reserved.
Table 2
- Register Memory Map
Address A[13:0]
Description
REG
#
STP
#1
STP
#2
STP
#3
STP
#4
00
0000
0001
0002
0800
0801
0802
1000
1001
1002
1800
1801
1802
STP Incoming Configuration
01
02
STP Outgoing Configuration
STP Input Signal Activity Monitor #1, Accumulation
Trigger
03
04
05
06
07
0003
0004
0005
0006
0007
0803
0804
0805
0806
0807
1003
1004
1005
1006
1007
1803
1804
1805
1806
1807
STP Reset and Identity
STP VTPP #1 Configuration #1
STP VTPP #2 Configuration #1
STP VTPP #3 Configuration #1
STP Tributary Payload Processor and LOM Interrupt
Enable
08
0008
0808
1008
1808
STP Tributary Payload Processor Interrupt and LOM
Status
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
107
PMC [ PMC-SIERRA, INC ]
