PM5361TUPP
DATA SHEET
PMC-920526
ISSUE 8
TRIBUTARY UNIT PAYLOAD PROCESSOR
Pin Name Type
Pin Function
No.
IPAR
Input
70
The incoming stream parity (IPAR) signal carries
the parity of the incoming signals. The parity
calculation encompasses the IC1J1 signal, the
ISPE signal and the DIN[7:0] bus. IC1J1 and
ISPE can be included in the parity calculation by
setting the INCIC1J1 and INCISPE register bits
respectively high. Odd parity is selected by
setting the IOP register bit high, and even parity
is selected by setting the IOP bit low. The
INCIC1J1, INCISPE and IOP bits are located in
the master incoming configuration register. IPAR
is sampled on the rising edge of SCLK.
OC1J1
Input
127 The outgoing C1/J1 frame pulse (OC1J1) marks
the transport envelope and synchronous payload
envelope frame boundaries on the DOUT[7:0]
bus. When the OJ1EN register bit is set low,
OC1J1 pulses high to mark the first C1 byte of
the transport envelope frame on the DOUT[7:0]
bus. The position of the J1 bytes is implicit and
fixed to the bytes immediately following the last
C1 byte.
When the OJ1EN register bit is set high, the
OC1J1 signal pulses high while ISPE is low to
mark the first C1 byte of the transport envelope
frame on the DOUT[7:0] bus and pulses high
while OSPE is high to mark each of the J1 bytes
of the synchronous payload envelope(s) on the
DOUT[7:0] bus. OC1J1 must be present at every
occurrence of the first C1 byte and all J1 bytes.
A V1 pulse added to the OC1J1 input will be
ignored by the TUPP.
The OJ1EN bit is located in the master outgoing
configuration register. OC1J1 is sampled on the
rising edge of SCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
13
PMC [ PMC-SIERRA, INC ]
