PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Register 0x03: S/UNI-622-MAX Clock Monitors
Bit
Bit 7
Type
Function
Default
R
R
R
R
R
R
R
R
TCLKA
RCLKA
X
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFCLKA
TFCLKA
Unused
REFCLKA
PICLKA
PTCLKA
This register provides activity monitoring of the S/UNI-622-MAX clocks. When a monitored clock
signal makes a low to high transition, the corresponding register bit is set high. The bit will
remain high until this register is read, at which point, all the bits in this register are cleared. A lack
of transitions is indicated by the corresponding register bit reading low. This register should be
read at periodic intervals to detect clock failures.
PTCLKA:
The PTCLK active (PTCLKA) bit monitors for low to high transition on the PTCLK parallel
transmit clock input. PTCLKA is set high on a rising edge of PTCLKI and is set low when this
register is read.
PICLKA:
The PICLK active (PICLKA) bit monitors for low to high transition on the PICLK parallel
receive clock input. PICLKA is set high on a rising edge of PICLKI and is set low when this
register is read.
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transition on the REFCLK CSU-
622 and CRU-622 reference clock input. REFCLKA is set high on a rising edge of REFCLKI
and is set low when this register is read.
TFCLKA:
The TFCLK active (TFCLKA) bit monitors for low to high transition on the TFCLK transmit
system interface clock input. TFCLKI is set high on a rising edge of PTLCKI and is set low
when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PMC [ PMC-SIERRA, INC ]
