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PM5356-BI 参数 Datasheet PDF下载

PM5356-BI图片预览
型号: PM5356-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM Network Interface, 1-Func, CMOS, PBGA304, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 278 页 / 1562 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PM5356  
S/UNI-622-MAX  
DATASHEET  
S/UNI-622-MAX  
PMC-1980589  
ISSUE 5  
SATURN USER NETWORK INTERFACE (622-MAX)  
Provides a differential PECL bit-serial interface at 622.08 Mbit/s.  
Inserts a register programmable path signal label (C2).  
Generates the transmit payload pointer (H1, H2) and inserts the path overhead.  
Scrambles the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 stream and inserts the framing bytes  
(A1, A2).  
Optionally inserts register programmable APS bytes.  
Provides a byte-serial transmit path data stream allowing two devices to implement 1+1 APS.  
Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-96 codes (B2), line  
remote error indications (REI-L), and section BIP-8 codes (B1) to allow performance monitoring at the  
far end.  
Allows forced insertion of all-zeros data (after scrambling) and the corruption of the section, line, or  
path BIP-8 codes for diagnostic purposes.  
Inserts ATM cells into the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 payload.  
1.5  
The Transmit ATM Processor  
Provides idle/unassigned cell insertion.  
Provides HCS generation/insertion, and ATM cell payload scrambling.  
Counts number of transmitted and idle cells.  
Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with  
parity support for writing cells into an internal four-cell FIFO.  
Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with  
parity support for writing cells into an internal four-cell FIFO.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERSINTERNAL USE  
3
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