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PM5356-BI 参数 Datasheet PDF下载

PM5356-BI图片预览
型号: PM5356-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM Network Interface, 1-Func, CMOS, PBGA304, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 278 页 / 1562 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PM5356  
S/UNI-622-MAX  
DATASHEET  
S/UNI-622-MAX  
PMC-1980589  
ISSUE 5  
SATURN USER NETWORK INTERFACE (622-MAX)  
Register 0x5C: CRSI Configuration  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
R/W  
R/W  
SDINV  
PFPEN  
SENB  
0
0
0
Reserved  
Unused  
LOTI  
0
X
X
X
X
R
R
R
ROOLI  
DOOLI  
DOOLI:  
The DOOLI bit is the data out of lock interrupt status bit. DOOLI is set high when the the  
DOOLV bit changes state, indicating that either the CRU has locked to the incoming data  
stream or has gone out of lock. DOOLI is cleared when this register is read.  
ROOLI:  
The ROOLI bit is the reference out of lock interrupt status bit. ROOLI is set high when the  
ROOLV register changes state, indicating that either the PLL is locked to the reference clock  
REFCLK or in out of lock. ROOLI is cleared when this register is read.  
LOTI:  
The LOTI bit is the loss of transition interrupt status bit. LOTI is set high when a loss of  
transition event occurs. A loss of transition is defined as either the SD input set low or more  
than 96 consecutive ones or zeros received. LOTI is cleared when this register is read.  
SENB:  
The loss of signal transition detector enable (SENB) bit enables the declaration of loss of  
transition (LOT) when more than 96 consecutive ones or zeros occurs in the receive data.  
When SENB is a logic zero, a loss of transition is declared when more than 96 consecutive  
ones or zeros occurs in the receive data or when the SD input is low. When SENB is a logic  
one, a loss of transition is declared only when the SD input is low.  
PFPEN:  
The parallel frame pulse enable (PFPEN) enables the parallel frame pulse operation when  
the parallel data interface is enabled (LIFSEL is set high). When PFPEN is a logic zero, the  
FPIN input is ignored and the SONET/SDH framing is performed on the PIN[7:0] data. When  
PFPEN is logic one, the SONET/SDH framer is ignored and the PIN[7:0] bus is assumed to  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERSINTERNAL USE  
149  
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