PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Register 0x5A: CSPI Clock Synthesis Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
Reserved
CSURESET
CSURESETLPF
Reserved
0
0
0
0
X
0
0
0
Unused
R/W
R/W
R/W
Reserved
Reserved
Reserved
The CSU Control register provides direct access to the CSU. When the CSU does not lock
properly (ROOLV remains high), the CSU may be re-initialized using this register.
When the AVD power supply of the S/UNI-622-MAX is subjected to a change greater than the
±5% tolerance specified for the 3.3V analog supply pins, the Clock Synthesis Unit may lose lock
to the reference clock. When this occurs, the ROOLV will remain high until the CSU is reset
using the CSURESETLPF and CSURSET registers.
The S/UNI-622-MAX will operate normally if the power supply does not vary beyond the specified
±5% tolerance.
CSURESETLPF:
The CSU low pass filter (LPF) reset control CSURESETLPF bit provides a software reset for
the CSU-622 ABC. When CSURESETLPF is set high, the CSU RESETLPF input is set high
forcing the CSU LPF into reset. When CSURESETLPF is set low, the CSU RESETLPF input
is controlled by the system reset.
The CSURESETLPF and CSURESET should be held high for 10ms to properly reset the
CSU.
CSURESET:
The CSU reset control CSURESET bit provides a software reset for the CSU-622 ABC.
When CSURESET is set high, the CSU RESET input is set high forcing the CSU into reset.
When CSURESET is set low, the CSU RESET input is controlled by the system reset and
digital test mode.
The CSURESETLPF and CSURESET should be held high for 10ms to properly reset the
CSU.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
148
PMC [ PMC-SIERRA, INC ]
