PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Register 0x30 (EXTD=1): RPOP Status/Control
Bit
Bit 7
Type
Function
Default
R/W
R/W
R/W
R/W
Reserved
IINVCNT
PSL5
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Reserved
Unused
0
X
X
X
X
R
R
ERDIV[2]
ERDIV[1]
ERDIV[0]
R/W
NOTE: To facilitate additional register mapping, shadow registers have been added to registers
0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal
registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing
the normal registers and the shadow registers.
The Status Register is provided at RPOP read address 0, if the extend register (EXTD) bit is set
in register 6.
ERDIV[2:0]:
The ERDIV[2:0] bits reflect the current state of the detected enhanced RDI, (filtered G1 bits 5,
6, & 7).
IINVCNT:
When a logic one is written to the IINVCNT (Intuitive Invalid Pointer Counter) bit, if in the LOP
state 3 x new point resets the inv_point count. If this bit is set to 0 the inv_point count will not
be reset if in the LOP state and 3 x new pointers are detected.
PSL5:
The PSL5 bit controls the filtering of the path signal label byte (C2). When PSL5 is set high,
the PSL is updated when the same value is received for 5 consecutive frames. When the
PSL5 is set low, the PSL is updated when the same value is received for 3 consecutive
frames.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PMC [ PMC-SIERRA, INC ]
