PM5345 S/UNI-155
DATA SHEET
PMC-930305
ISSUE 4
SATURN USER NETWORK INTERFACE
Pin Name Type
Pin
Function
No.
PICLK
I/O
153
The parallel input clock (PICLK) provides
timing for sampling the received SONET STS-
3c (STM-1) stream that is input by the S/UNI
when the byte serial interface is selected
(RSER is tied low). This clock provides timing
for S/UNI receive function operation. PICLK is
nominally a 19.44 MHz, 50% duty cycle clock.
PIN[7:0] and FPIN are sampled on the rising
edge of PICLK. RCLK is a buffered version of
PICLK when the byte serial interface is
selected. When the 155 Mbit/s serial interface
is selected (RSER is tied high), PICLK
becomes an output and must not be driven.
RX_VCLK
The test vector clock (RX_VCLK) signal is
used during S/UNI production testing to verify
internal functionality.
PIN[0]
PIN[1]
PIN[2]
PIN[3]
PIN[4]
PIN[5]
PIN[6]
PIN[7]
Input
144
145
146
147
148
149
150
151
11
The data input (PIN[7:0]) bus carries the STS-
3c (STM-1) stream when the byte serial
interface is selected (RSER is tied low).
PIN[7:0] is sampled on the rising edge of
PICLK. PIN[7] is the most significant bit
(corresponding to bit 1 of each serial word, the
first bit transmitted). PIN[0] is the least
significant bit (corresponding to bit 8 of each
word, the last bit transmitted).
FPOS/MLT Input
The dual function input (FPOS/MLT) selects
both the transmit encoding scheme and the
receive frame pulse location depending on the
line side interface selected using inputs TSER
and RSER.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
17
PMC [ PMC-SIERRA, INC ]
