PM5345 S/UNI-155
DATA SHEET
PMC-930305
ISSUE 4
SATURN USER NETWORK INTERFACE
ATM cells are written to an internal four cell FIFO using a generic 9 bit wide or 17
bit wide datapath interface. Idle/unassigned cells are automatically inserted
when the internal FIFO contains less than one cell. The S/UNI provides
generation of the header check sequence and scrambles the payload of the ATM
cells. Each of these transmit ATM cell processing functions can be enabled or
bypassed.
No auxiliary clocks are required directly by the S/UNI as it operates from two
155.52 MHz clocks (bit serial line interface) or two 19.44 MHz clocks (byte serial
interface). The S/UNI is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI also provides a standard 5 signal
P1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI is implemented in low power, +5 Volt, CMOS technology. It has TTL
and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a
160 pin PQFP package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
