Pm49FL002 / 004
PMC
LPC MODE OPERATION (CONTINUED)
LPC BYTE PROGRAM WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Write
Address
11xxb
0101b
Load "5555h" in 8 Clocks
Data
1010b
TAR
Tri-State
Clocks
Sync
TAR
1111b
Tri-State
1st Start
0000b
Cycle
1111b
1111b
1111b
1111b
1111b
1111b
1111b
1111b
0101b
1010b
Clocks
1111b
2
0000b
011Xb
1111b
0101b
0101b
LAD[3:0]
1
Clock
2
Clocks
Load "AAh" in
2
1
Clock
1
1
1
1
Clock
Host to Device
Device to Host
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
Memory
Write
Cycle
Address
11xxb
Load "2AAAh" in 8
Data
TAR
Tri-State
Clocks
Sync
TAR
Tri-State
Clocks
2nd Start
0000b
1010b
0101b
0101b
Clocks
011Xb
Clock
1111b
0010b
Clocks
1010b
1010b
0101b
A[3:1]
1111b
2
0000b
1111b
1
Clock
2
Load "55h" in
2
1
Clock
Host to Device
Device to Host
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
Memory
Write
Cycle
Address
11xxb
0101b
Load "5555h" in 8 Clocks
Data
TAR
Tri-State
Clocks
Sync
TAR
3rd Start
0000b
0000b
1010b
1111b
2
0000b
1111b
Tri-State
011Xb
Clock
1111b
0101b
0101b
1
Clock
2
Clocks
Load "A0h" in
2
Clocks
1
Clock
Host to Device
Device to Host
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
Memory
Write
Cycle
Address
A[15:12]
A[19:16]
Load Address in 8 Clocks
Data
TAR
Tri-State
Clocks
Sync
TAR
4th Start
0000b
A[11:8]
D[3:0]
D[7:4]
Tri-State
Clocks
011Xb
Clock
1111b
A[7:4]
1111b
2
0000b
1111b
1
Clock
2
Load Data in
2
Clocks
1
Clock
Host to Device
Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
19