Pm49FL002 / 004
PMC
LPC MODE OPERATION (CONTINUED)
Table 5: LPC Memory Write Cycle Definition
Clock Cycle
Field
LAD[3:0] Direction Description
Start of Cycle: "0000b" to indicate the start of a LPC
memory cycle.
1
START
0000
IN
Cycle Type: Indicates the type of a LPC memory write cycle.
CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR:
Bit 1 = "1b" indicates the type of cycle for Write. Bit 0 is
reserved.
CYCTYPE
2
+
DIR
011x
IN
Address Cycles: This is the 32-bit memory address. The
addresses transfer most-significant nibble first and least-
significant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3
- A0 on LAD[3:0] last).
3 - 10
ADDR
DATA
YYYY
IN
IN
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on
LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last).
11 - 12
YYYY
1111
IN then
Float
Turn-Around Cycle 0: The Chipset has driven the bus to all
"1"s and then float the bus.
13
14
15
16
17
TAR0
TAR1
SYNC
TAR0
TAR1
1111
(float)
Float then Turn-Around Cycle 1: The device takes control of the bus
OUT
during this cycle.
Sync: The device indicates that it has received the data or
command.
0000
1111
OUT
OUT then Turn-Around Cycle 0: The device has driven the bus to all
Float "1"s and then floats the bus.
Float then Turn-Around Cycle 1: The Chipset resumes control of the bus
IN during this cycle.
1111
(float)
LPC MEMORY WRITE CYCLE WAVEFORMS
CLK
RST# or INIT#
LFRAME#
Memory
Write
Cycle
Address
Data
Next Start
0000b
Start
SYNC
0000b
TAR
TAR
1111b
1111b
A[19:16]
A[7:4]
D[3:0]
D[7:4]
1111b
2
0000b
Clock
011Xb
Clock
1111b
A[15:12]
Clocks
A[11:8]
A[3:0]
Tri-State
1111b Tri-State
LAD[3:0]
1
1
Clocks
1
Clock
2
Clocks
1 Clock
Load Data in
2
Clocks
Load Address in
8
From Host to Device
From Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
18