Pm49FL002 / 004
PMC
FWH MODE OPERATION (CONTINUED)
FWH BYTE PROGRAM WAVEFORMS
CLK
RST# or INIT#
FWH4
Memory
Write
Address
0101b
Load "5555h" in
Data
1010b
TAR
Tri-State
Clocks
RSYNC
0000b
TAR
1111b
Tri-State
IDSEL
ID[3:0]
IMSIZE
0000b
Cycle
xxxxb
xxxxb
xxxxb
xxxxb
1010b
1111b
2
1110b
x1xxb
x1xxb
x1xxb
x1xxb
xxxxb
0101b
Clocks
0101b
0101b
FWH[3:0]
CLK
1
Clock
2
Clocks
1
Clock
1
Clock
7
7
7
1
Clock Load "AAh" in
2
Clocks
Host to Device
Device to Host
RST# or INIT#
FWH4
2nd Start
1110b
IMSIZE
0000b
Address
0010b
Load "2AAAh" in
Data
TAR
Tri-State
Clocks
RSYNC
0000b
TAR
Tri-State
Clocks
IDSEL
ID[3:0]
Clock
1010b
0101b
0101b
xxxxb
1010b
Clocks
1010b
1111b
2
1111b
FWH[3:0]
1
Clock
2
1
Clock
1
1
1
1
Clock Load "55h" in
2
Clocks
Host to Device
Device to Host
CLK
RST# or INIT#
FWH4
IMSIZE
0000b
Address
0101b
Load "5555h" in
Data
TAR
Tri-State
Clocks
RSYNC
0000b
TAR
3rd Start
1110b
IDSEL
ID[3:0]
Clock
0000b
1010b
1111b
2
1111b
Tri-State
xxxxb
0101b
Clocks
0101b
0101b
FWH[3:0]
1
Clock
2
Clocks
1
Clock
1
Clock Load "A0h" in
2
Clocks
Host to Device
Device to Host
CLK
RST# or INIT#
FWH4
IDSEL
ID[3:0]
Clock
IMSIZE
0000b
Clock
Address
A[19:16] A[15:12]
Load Address in
Data
TAR
Tri-State
Clocks
RSYNC
0000b
TAR
4th Start
1110b
A[11:8]
Clocks
A[7:4]
A[3:1]
D[3:0]
Load Data in
D[7:4]
Tri-State
Clocks
1111b
2
1111b
FWH[3:0]
1
Clock
2
2
Clocks
1
Clock
7
1
Host to Device
Device to Host
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
12
PMC [ PMC-SIERRA, INC ]
