STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
B8ZS and HDB3 decoding, line code violation detection, and loss of signal
detection. It recovers the clock from the incoming RZ data pulses using a digital
phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated
after a programmable threshold of consecutive bit periods of the absence of
pulses on both the positive and negative line pulse inputs and is cleared after the
occurrence of a single line pulse. An alternate loss of signal indication is
provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1
and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt
is generated when a loss of signal is detected and when the signal returns. A
line code violation is defined as a bipolar violation (BPV) for AMI-coded signals,
is defined as a BPV that is not part of a zero substitution code for B8ZS-coded
signals, and is defined as a bipolar violation of the same polarity as the last
bipolar violation for HDB3-coded signals.
In T1 mode, the input jitter tolerance of the COMET complies with the Bellcore
Document TA-TSY-000170 and with the AT&T specification TR62411, as shown
in Figure 6. The tolerance is measured with a QRSS sequence (220-1 with 14
zero restriction). The CDRC block provides two algorithms for clock recovery
that result in differing jitter tolerance characteristics. The first algorithm (when the
ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but
the high frequency tolerance is close to the TR62411 limit. The second algorithm
(when ALGSEL is logic 1) provides much better high frequency jitter tolerance at
the expense of the low frequency tolerance; the low frequency tolerance of the
second algorithm is approximately 80% that of the first algorithm.
PROPRIETARY AND CONFIDENTIAL
36
PMC [ PMC-SIERRA, INC ]
