STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No.
Function
-RI
50
-NI
BRSIG
Output
with
F7
Backplane Receive Signaling (BRSIG). BRSIG contains the extracted
signaling bits for each channel in the frame, repeated for the entire superframe.
Each channel's signaling bits are valid in bit locations 5, 6, 7 and 8 of the
channel and are channel-aligned with the BRPCM data stream. When the RX-
ELST is not by-passed, the BRSIG stream is aligned to the backplane input
timing. When BRCLK is either 4.096 MHz, 8.192 MHz or 16.384 MHz, BRSIG
can be tristated and is only active during programmable timeslots to allow byte
interleaving of signaling data streams from up to 4 COMET devices with no
external logic.
Tristate
After a reset, BRSIG is high impedance.
BRSIG is updated on the active edge of BRCLK.
Table 3
- Transmit Line Interface (6 pins)
Pin Name
Type
Pin No.
-RI -NI
D5
Function
TXTIP1
TXTIP2
Analog
Output
73
79
Transmit Analog Positive Pulse (TXTIP1 and TXTIP2). When the transmit
analog line interface is enabled, the TXTIP1 and TXTIP2 analog outputs drive
the transmit line pulse signal through an external matching transformer. Both
TXTIP1 and TXTIP2 are normally connected to the positive lead of the
transformer primary. Two outputs are provided for better signal integrity and
should be shorted together on the board.
A2
After a reset, TXTIP1 and TXTIP2 are high impedance. The HIGHZ bit of the
XLPG Line Driver Configuration register (address 0F0H) must be programmed
to logic 0 to remove the high impedance state.
TXRING1
TXRING2
Analog
Output
72
80
C5
C4
Transmit Analog Negative Pulse (TXRING1 and TXRING2). When the transmit
analog line interface is enabled, the TXRING1 and TXRING2 analog outputs
drive the transmit line pulse signal through an external matching transformer.
Both TXRING1 and TXRING2 are normally connected to the negative lead of
the transformer primary. Two outputs are provided for better signal integrity
and should be shorted together on the board.
After a reset, TXRING1 and TXRING2 are high impedance. The HIGHZ bit of
the XLPG Line Driver Configuration register (address 0F0H) must be
programmed to logic 0 to remove the high impedance state.
TDAT
Digital
Output
6
C2
Transmit Digital PCM Data (TDAT). When the transmit digital line interface is
enabled, the TDAT output provides the line side NRZ PCM transmit data. This
mode may be used in applications not requiring a physical T1/E1 interface (e.g.
interfacing to HDSL transceivers). TDAT is updated on the either the rising or
falling (default) edge of TCLKO.
PROPRIETARY AND CONFIDENTIAL
23
PMC [ PMC-SIERRA, INC ]
