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PM4351-NI 参数 Datasheet PDF下载

PM4351-NI图片预览
型号: PM4351-NI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
signal and greater than 7 bits long for a B8ZS-coded signals. The inclusion of  
excessive zeros in the line code violation count can be disabled.  
For E1, a line code violation is defined as a bipolar violation (BPV) for AMI-coded  
signals and is defined as a bipolar violation of the same polarity as the last  
bipolar violation for HDB3-coded signals.  
Generation of the transfer clock within the COMET chip is performed by writing  
to any counter register location or by writing to the Global PMON Update register.  
The holding register addresses are contiguous to facilitate faster polling  
operations.  
9.8  
T1 Bit Oriented Code Detector (RBOC)  
The Bit Oriented Code detection function is provided by the RBOC block. This  
block detects the presence of 63 of the possible 64 bit oriented codes  
transmitted in the Facility Data Link channel in ESF framing format, as defined in  
th  
ANSI T1.403-1993 and in TR-TSY-000194. The 64 code (111111) is similar to  
the DL FLAG sequence and is used by the RBOC to indicate no valid code  
received.  
Bit oriented codes are received on the Facility Data Link channel as a 16-bit  
sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero  
(111111110xxxxxx0) which is repeated at least 10 times. The RBOC can be  
enabled to declare a received code valid if it has been observed for 8 out of 10  
times or for 4 out of 5 times, as specified by the AVC bit in the control register.  
Valid BOC are indicated through an internal status register. The BOC bits are set  
to all ones (111111) if no valid code has been detected. An interrupt is generated  
to signal when a detected code has been validated, or optionally, when a valid  
code goes away (i.e. the BOC bits go to all ones).  
9.9  
HDLC Receiver (RDLC)  
The HDLC Receiver function is provided by the RDLC block. The RDLC is a  
microprocessor peripheral used to receive HDLC frames. Three RDLC blocks  
are provided for flexible extraction of standardized data links:  
T1 ESF facility data link  
T1DM data link  
ISDN D-channel  
E1 Common Channel Signaling data link  
PROPRIETARY AND CONFIDENTIAL  
48