STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 032H: BRIF Parity/F-bit Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
RPTYP
RPTYE
FIXF
0
0
0
0
0
X
0
0
FIXPOL
PTY_EXTD
Unused
TRI[1]
R/W
R/W
TRI[0]
This register provides control of data integrity checking on the receive backplane
interface. A single parity bit in the F-bit position represents parity over the
previous frame (including the undefined bit positions). If a 2.048 Mbit/s
backplane rate is selected, the parity calculation is performed over all bit
positions, including the undefined positions. Signaling parity is similarly
calculated over all bit positions. Parity checking and generation is not supported
when the NxDS0 mode is active. Parity checking and generation is not
supported when mapping a 1.544 Mbit/s signal onto a higher rate backplane in
the format where the first 24 time slots are used, i.e., the RATE[1:0] bits in the
BRIF Configuration register are not set to “00” and the MAP bit in the BRIF
Frame Pulse Configuration register is logic 1.
RPTYP:
The receive parity type (RPTYP) bit sets even or odd parity in the receive
streams. If RPTYP is a logic 0, the expected parity value in the F-bit position
of BRPCM and BRSIG is even, thus it is a one if the number of ones in the
previous frame is odd. If RPTYP is a logic 1, the expected parity value in the
F-bit position if BRPCM and BRSIG is odd, thus it is a one if the number of
ones in the previous frame is even. RPTYP only has effect if RPRTYE is a
logic one.
RPRTYE:
The RPRTYE bit enables receive parity insertion. When set a logic one,
parity is inserted into the F-bit position of the BRPCM and BRSIG streams.
When set to logic zero, the F-bit passes through transparently.
PROPRIETARY AND CONFIDENTIAL
144
PMC [ PMC-SIERRA, INC ]
