PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 32H:TPSC Channel Indirect Address/Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/WB
A6
0
0
0
0
0
0
0
0
A5
A4
A3
A2
A1
A0
This register allows the µP to access the internal TPSC registers addressed by
the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this
register with a valid address and R/WB bit initiates an internal µP access request
cycle.The R/WB bit selects the operation to be performed on the addressed
register: when R/WB is set to a logic 1, a read from the internal TPSC register is
requested; when R/WB is set to a logic 0, an write to the internal TPSC register
is requested.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
130
PMC [ PMC-SIERRA, INC ]
