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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
66  
67  
S
3
undefined  
S
S
S
S
S
90  
91  
S
21  
undefined  
S
S
S
S
S
127  
undefined  
12.12 Serial Clock and Data Format  
The Serial Clock and Data interfaces are able to carry the complete payload for  
28 T1s or 21 E1s. Each T1 or E1 is assigned to one transmit pin and one  
receive data pin for the payload. As appropriate, additional pins may exist for the  
T1/E1 clock, signaling bits and/or frame pulse, depending on the specific  
interface mode selected. The formatting of these bits is outlined in greater deail  
in the Functional Timing section of this document.  
In T1 mode, all 28 sets of clock and data pins are used in each direction.  
In normal E1 mode, the first 21 sets of clock and data pins are used in each  
direction. The clock and data pins numbered between 22 and 28 are not  
defined, as the 22nd through 28th framer blocks are not used in this mode.  
In ITU-T G.747 mutiplexed E1 mode, every fourth set of clock and data pins are  
not used in each direction. (i.e. Pins 1-3, 5-7, 9-11, 13-15, 17-19, 21-23, 25-27  
are defined while pins 4, 8, 12, 16, 20, 24, and 28 are not defined.) This is  
because the 4th, 8th, 12th, 16th, 20th, 24th and 28th framer blocks are not used in  
this mode.  
12.13 PRGD Pattern Generation  
The pattern generator can be configured to generate pseudo random patterns or  
repetitive patterns as shown in Figure 41 below:  
PROPRIETARY AND CONFIDENTIAL  
170  
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