PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
:
Write data for WAVEFORM=0, SAMPLE=0, UI=0
Write data for WAVEFORM=0, SAMPLE=0, UI=1
Write data for WAVEFORM=0, SAMPLE=0, UI=2
Write data for WAVEFORM=0, SAMPLE=0, UI=3
Write data for WAVEFORM=0, SAMPLE=0, UI=4
Write data for WAVEFORM=1, SAMPLE=12, UI=0
Write data for WAVEFORM=1, SAMPLE=12, UI=1
Write data for WAVEFORM=1, SAMPLE=12, UI=2
Write data for WAVEFORM=1, SAMPLE=12, UI=3
Write data for WAVEFORM=1, SAMPLE=12, UI=4
:
whereas the following sequence fragment is illegal:
:
Write data for WAVEFORM=0, SAMPLE=0, UI=0
Write data for WAVEFORM=0, SAMPLE=1, UI=0
Write data for WAVEFORM=0, SAMPLE=2, UI=0
Write data for WAVEFORM=0, SAMPLE=3, UI=0
Write data for WAVEFORM=0, SAMPLE=4, UI=0
Write data for WAVEFORM=0, SAMPLE=5, UI=0
Write data for WAVEFORM=0, SAMPLE=6, UI=0
Write data for WAVEFORM=0, SAMPLE=7, UI=0
Write data for WAVEFORM=0, SAMPLE=8, UI=0
Write data for WAVEFORM=0, SAMPLE=9, UI=0
:
This restriction is necessary because each group of five 7-bit samples is stored in a temporary
holding register as it is written. The 5 samples are then transferred to the pulse template RAM as
a single 35-bit word when the 5th sample (i.e. the sample whose UI[2:0] address field is set to 4)
is written.
Prior to commencing normal operation, the HIGHZ bit of the octant’s XLPG Line Driver
Configuration register must be programmed to logic 0 to remove the high impedance state from
the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] Transmit outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
174
PMC [ PMC-SIERRA, INC ]
