PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
11
TEST FEATURES DESCRIPTION
Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus
to be held in a high-impedance state. This test feature may be used for board testing.
11.1 JTAG Test Port
The OCTLIU JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP
registers: instruction, bypass, device identification and boundary scan. Using the TAP, device
input logic levels can be read, device outputs can be forced, the device can be identified and the
device scan path can be bypassed. For more details on the JTAG port, please refer to the
Operations section.
Instruction Register
Length – 3 bits
Instructions
Selected Register
Instruction Codes,
IR[2:0]
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Boundary Scan
Identification
Boundary Scan
Bypass
000
001
010
011
100
101
110
111
Bypass
Boundary Scan
Bypass
Bypass
Identification Register
Length – 32 bits
Version number – 0H for Rev A.
Part Number – 4318H
Manufacturer’s identification code – 0CDH
Device identification – 043180CDH for Rev. A
Boundary Scan Register
Length – 131
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
169
PMC [ PMC-SIERRA, INC ]
