PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Pin Name
Type
Pin
No.
Function
CLKO8X/
Output 86
8X Clock Output (CLKO8X).
This output is the internal 8X high-speed clock
derived from the digital jitter attenuator, or
derived by dividing down the 24X XCLK input. It
is used as the reference clock to generate the
transmit analog pulse template. The CLKO8X
signal is generated from Quadrant 1.
1X Clock Output (CLKO1X).
CLKO1X
DCR
Output
When an 8X clock is provided on XCLK, this is
the internal 8X clock divided by 8. This output
can be used to synchronously clock in data on
TDP[4:1]/TDD[4:1] and TDN[4:1] by connecting it
to TCLKI[4:1].
Input
Input
37
66
Disable Clock Recovery Input (DCR). When set
high, the DCR input will disable clock recovery in
the QDSX and enable the SDP[4:1] and SDN[4:1]
sliced line pulse outputs. This input is logically
"ORed" with the DCR register bits.
TDUAL
Transmit Dual-Rail Input Select (TDUAL). This
input selects whether the QDSX expects single-
rail or dual-rail input transmit data. The TDUAL
input is logically "ORed" with the TDUAL register
bits. When TDUAL is set high, the TDP[4:1] and
TDN[4:1] inputs are enabled. When both the
TDUAL input pin and register bits are set low,
then the TDD[4:1] inputs are enabled and the
TDN[4:1] inputs are ignored.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
PMC [ PMC-SIERRA, INC ]
