PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
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Detects unframed 2 -1 test sequences as defined in ITU-T O.151 and
accumulates bit errors detected using this pseudo-random pattern.
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Optionally inserts unframed 2 -1 test sequences in place of recovered data.
Each transmitter section
Generates DSX-1 and CEPT E1 compatible pulses with programmable pulse
shape using an external 1:1.36 turns ratio transformer.
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Accommodates standard cable types such as ABAM, PIC, and Coaxial.
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Provides an integrated analog pulse driver performance monitor which can
provide an interrupt upon detection of failure.
Allows bipolar violation (BPV) transparent operation for error restoring
regenerator applications.
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Allows bipolar violation (BPV) insertion for diagnostic testing purposes.
Supports all ones transmission for alarm indication signal (AIS) generation.
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Provides a digital phase-locked loop for generation of jitter reduced transmit
output timing. The DPLL utilizes a 37.056 MHz master clock for DSX-1 or a
49.152 MHz master clock for CEPT E1 applications.
Digital phase-locked loop locks 1.544 MHz or 2.048 MHz output timing to the
average frequency of the 1.544 MHz or 2.048 MHz jittered transmit input
clock.
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Provides a 2 x 48 bit FIFO for jitter attenuation in the transmit path.
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Provides up to 55 dB of jitter attenuation to satisfy AT&T TR 62411, ITU-T
G.737, G.738, G.739, and G.742.
Provides FIFO overrun and underrun indicators.
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Inhibits FIFO overrun and underrun for excessive jitter amplitudes.
Supports transmission of a programmable unframed inband loopback code
sequence.
Programmable to transmit repetitions of any arbitrary code from three to eight
bits in length.
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Accepts either dual rail or single rail DS-1/E1 signals.
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Performs B8ZS or AMI encoding when processing a single rail DS-1 signal
and HDB3 or AMI encoding when processing a single rail E1 signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
3
PMC [ PMC-SIERRA, INC ]
