PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
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FEATURES
Integrates four duplex DSX-1 or CEPT E1 compatible line interface circuits in
a single monolithic device. Line format is selected on a per-device basis.
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Provides clock recovery and line performance monitoring in the receivers.
Provides jitter attenuation and programmable line build out in the transmitters.
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Utilizes digital phase-locked loops for receive and transmit clock derivation
without the use of tuned circuits.
Provides an integrated 8X clock multiplier for generation of required high-
speed clocks in applications not requiring jitter attenuation.
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Optionally inserts Alarm Indication Signal (AIS) when loopback modes are
enabled. AIS insertion may also be directly controlled via the microprocessor
interface.
Provides a generic microprocessor interface for initial configuration, ongoing
control, and status monitoring.
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Generates an interrupt upon detection of any of various alarms, events, or
changes in status. Identification of interrupt sources, masking of interrupt
sources, and acknowledgment of interrupts is provided via internal registers.
Provides optional hardware programmed mode which provides external
configuration pins when microprocessor access is not available to the device.
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Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
Provides seamless interface to PM4344 TQUAD, PM6344 EQUAD, PM8313
D3MX, and PM7344 S/UNI-MPH.
Low power CMOS technology, 1500 mW power dissipation processing all
ones signals on all four quadrants.
128-pin (14mm x 20mm) PQFP package.
Each receiver section
Slices incoming G.703 DSX-1 and CEPT E1 bipolar line signals into digital
return-to-zero (RZ) pulses.
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Selectable slicer levels (DSX-1/CEPT E1) to provide improved SNR.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
