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HDMP-1638G 参数 Datasheet PDF下载

HDMP-1638G图片预览
型号: HDMP-1638G
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, Bipolar, PQFP64,]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 18 页 / 266 K
品牌: PMC [ PMC-SIERRA, INC ]
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Frame Demux and Byte Sync  
characters must not be  
transmitted in consecutive bytes  
to allow the receiver byte clocks  
to maintain their proper  
The FRAME DEMUX AND BYTE  
SYNC block is responsible for  
restoring the 10-bit parallel  
recovered frequencies.  
data from the high speed serial bit  
stream. This block is also  
Output Drivers  
responsible for recognizing the  
comma character (or a K28.5  
character) of positive disparity  
(0011111xxx). When recognized,  
the FRAME DEMUX AND BYTE  
SYNC block works with the RX  
PLL/CLOCK RECOVERY block  
to properly align the receive byte  
clocks to the parallel data. When a  
comma character is detected and  
realignment of the receiver byte  
clocks (RBC1/RBC0) is necessary,  
these clocks are stretched, not  
slivered, to the next possible  
correct alignment position. These  
clocks will be fully aligned by the  
start of the second 2-byte ordered  
set. The second comma character  
received shall be aligned with the  
rising edge of RBC1. As per the  
8B/10B encoding scheme, comma  
The OUTPUT DRIVERS present  
the 10-bit parallel recovered data  
byte properly aligned to the  
receive byte clocks (RBC1/RBC0),  
as shown in Figure 5. These  
output data buffers provide TTL  
compatible signals.  
Signal Detect  
The SIGNAL DETECT block  
examines the differential  
amplitude of the inputs DINB.  
When this input signal is too  
small, it outputs a logic 0 at  
SIG_DET (refer to SIG_DET pin  
definition for detection  
thresholds). When the signal at  
DINB is of a valid amplitude,  
SIG_DET is set to logic 1.  
HDMP-1638G (Transmitter Section) Timing Characteristics  
T = 0°C to +70°C, V = 3.15 V to 3.45 V  
A
CC  
Symbol  
Parameter  
Units  
nsec  
nsec  
nsec  
bits  
Min.  
1.5  
Typ.  
Max.  
t
t
Setup Time  
Hold Time  
setup  
hold  
1.0  
[1]  
t_txlat  
Transmitter Latency  
3.5  
4.4  
Note:  
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of  
the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and  
the transmission of the first serial bit of that parallel word at either output pair (defined by the  
rising edge of the first bit transmitted).  
4
PMC-Sierra, Inc. - Not Recommended for New Designs  
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