The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two
62.5 MHz receiver byte clocks
which are 180 degrees out of
phase with each other. The
parallel data is properly aligned
with the rising edge of alternating
clocks.
HDMP-1638G
TRANSMITTER SECTION
PLL
SERIAL DATA OUT
PROTOCOL DEVICE
PLL
SERIAL DATA IN
RECEIVER SECTION
BYTSYNC
For test purposes, the transceiver
provides for on-chip local loop-
back functionality controlled
REFCLK
RXSEL
ENBYTSYNC
through an eternal input pin.
Additionally, the byte synchro-
nization feature may be disabled.
This may be useful in proprietary
applications which use alternative
methods to align the parallel data.
Figure 1. Typical application using the HDMP-1638G.
HDMP-1638G Block Diagram
The HDMP-1638G was designed
to transmit and receive 10-bit
wide parallel data over high-speed
serial lines. The parallel data
applied to the transmitter is
expected to be encoded per the
Gigabit Ethernet specification,
which uses an 8B/10B encoding
scheme with special reserve
characters for link management
purposes. In order to accomplish
this task, the HDMP-1638G
± DOUTA
± DOUTB
DATA BYTE
TX[0-9]
FRAME
MUX
OUTPUT
SELECT
INTERNAL
LOOPBACK
LOOPEN
TX
INTERNAL
TX CLOCKS
TXCAP0
TXCAP1
± DINA
± DINB
INPUT
SELECT
PLL/CLOCK
GENERATOR
± REFCLK
RX
RXCAP0
RXCAP1
RBC0
incorporates the following:
PLL/CLOCK
RECOVERY
RBC1
• TTL Parallel I/Os
• High Speed Phase Locked Loops
• Parallel to Serial Converter
• Serial Clock and Data Recovery
• Comma Character Recognition
• Byte Alignment Circuitry
• Serial to Parallel Converter
INTERNAL
RX CLOCKS
FRAME
DEMUX
AND
DATA BYTE
RX[0-9]
INPUT
SAMPLER
BYTE SYNC
BYTSYNC ENBYTSYNC
RXSFI
Figure 2. HDMP-1638G transceiver block diagram.
2
PMC-Sierra, Inc. - Not Recommended for New Designs
PMC [ PMC-SIERRA, INC ]
