PEX 8724, PCI Express Gen 3 Switch, 24 Lanes, 6 Ports
Error Injection & SerDes Loopback
Using the PEX 8724’s Error Injection feature, users can
inject malformed packets and/or fatal errors into their
system and evaluate a system’s ability to detect and
recover from such errors. The PEX 8724 also supports
Internal Tx, External Tx, Recovered Clock, and Recovered
Data Loopback modes.
failing CPU and enumerate them in its own domain
without impacting the operation of endpoints already in its
domain.
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
x4
x4s
x4
Applications
Suitable for
host-centric
as well as
peer-to-peer traffic
patterns,
the PEX 8724 can be configured for a wide
variety of form factors and applications.
PEX 8724
x4s
Endpoint
Endpoint
Endpoint
PEX 8724
x4s
Endpoint
Endpoint
x4
Host Centric Fan-out
The PEX 8724, with its symmetric or asymmetric lane
configuration capability, allows user-specific tuning to a
variety of host-centric applications. Figure 6 shows a
server design where, in a quad or multi processor system,
users can assign endpoints/slots to CPU cores to distribute
the system load. The packets directed to different CPU
cores will go to different (user assigned) PEX 8724
upstream ports, allowing better queuing and load balancing
capability for higher performance. Conversely, the PEX
8724 can also be used in single-host mode to simply fan-
out to endpoints.
CPU
CPU
CPU
Figure 7. Host Fail-Over
Fail-Over in Storage Systems with Multicast
The PEX 8724’s Multicast feature can be used to
simultaneously send redundant packets to a backup system
(Figure 8). In the example below, using Multicast (yellow
lines), the CPU sends data to its endpoints as well as to a
backup system (via an NT port) in one transaction as
opposed to having to send multiple transactions to each
endpoint. By offloading the task of backing up data onto
the secondary system, processor and system performance
is enhanced.
Backup
System
PCH
CPU
Memory
PCI
x4
x1s
x8
SATA
PEX 8724
CPU
CPU
CPU
CPU
CPU
CPU
Endpoint
x2s
x4s
CPU
Memory
CPU
Memory
x8
x8
NT
x8
PCIe Gen1, Gen2, or Gen3 slots
PEX 8724
x4
x4
x4
PEX
8724
Figure 6. Host Centric Dual Upstream
Host Failover
The PEX 8724 can also be utilized in applications where
host failover is required. In the below application (Figure
7), two hosts may be active simultaneously and controlling
their own domains while exchange status information
through doorbell registers or I
2
C interface. The devices can
be programmed to trigger fail-over if the heartbeat
information is not provided. In the event of a failure, the
surviving device will reset the endpoints connected to the
© PLX Technology, www.plxtech.com
Page 4 of 5
NT
NT
PEX 8716
x4
FC
Control
PEX 7616
x4
FC
Control
x4
FC
Control
x4
FC
Control
8 Disk Chassis
8 Disk Chassis
Figure 8. N+1 Failover
10/7/2010, Version 1.0
Endpoint
PLX [ PLX TECHNOLOGY ]
