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PEX8724-BA80BCG 参数 Datasheet PDF下载

PEX8724-BA80BCG图片预览
型号: PEX8724-BA80BCG
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC]
分类和应用:
文件页数/大小: 5 页 / 329 K
品牌: PLX [ PLX TECHNOLOGY ]
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PEX 8724, PCI Express Gen 3 Switch, 24 Lanes, 6 Ports
The PEX 8724 can also be configured in Multi-Host mode
where users can choose up to four ports as host/upstream
ports and assign a desired number of downstream ports to
each host. In Multi-Host mode, a virtual switch is created
for each host port and its associated downstream ports
inside the device. The traffic between the ports of a virtual
switch is completely isolated from the traffic in other
virtual switches. Figure 2 illustrates some configurations
of the PEX 8724 in Multi-Host mode where each ellipse
represents a virtual switch inside the device.
x4
x8
x4
x4
The PEX 8724
also provides
several ways to
configure its
PEX 8724
PEX 8724
registers. The
device can be
configured through
2 x4 2 x4
2 x4 2 x2
strapping pins,
I
2
C
x4
x8
x4
x2
interface,
host
software, or an
optional serial
PEX 8724
PEX 8724
EEPROM. This
allows for easy
debug during the
2 x2 2 x2
2 x4 2 x1
development
Figure 2. Multi-Host Port Configurations
phase,
performance monitoring during the operation phase, and
driver or software upgrade.
Multi-Host & Failover Support
In Multi-Host mode, PEX 8724 can be configured with up
to four upstream host ports, each with its own dedicated
downstream ports. The device can be configured for 1+1
redundancy or N+1 redundancy. The PEX 8724 allows the
hosts to communicate their status to each other via special
door-bell registers. In failover mode, if a host fails, the
host designated for failover will disable the upstream port
attached to the failing host and program the downstream
ports of that host to its own domain. Figure 4a shows a two
host system in Multi-Host mode with two virtual switches
inside the device and Figure 4b shows Host 1 disabled
after failure and Host 2 having taken over all of Host 1’s
end-points.
Host
1
Host
2
Host
1
Host
2
PEX 8724
PEX 8724
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
End
Point
Figure 4a. Multi-Host
Figure 4b. Multi-Host Fail-Over
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering down
the system. The PEX 8724 hot plug capability feature
makes it suitable for
High Availability (HA)
applications.
Three downstream ports include a Standard
Hot Plug Controller. If the PEX 8724 is used in an
application where one or more of its downstream ports
connect to PCI Express slots, each port’s Hot Plug
Controller can be used to manage the hot-plug event of its
associated slot. Every port on the PEX 8724 is equipped
with a hot-plug control/status register to support hot-plug
capability through external logic via the I
2
C interface.
Dual-Host & Failover Support
In Single-Host mode, the PEX 8724 supports a
Non-
Transparent (NT) Port,
which enables the
implementation of
Primary Host
Secondary Host
Primary Host
Secondary Host
dual-host systems
for
CPU
CPU
redundancy and host
failover capability. The
Root
NT port allows systems
Complex
to isolate host memory
domains by presenting
NT
the processor subsystem
PEX 8724
Non-Transparent
as an endpoint rather
Port
than another memory
End
End
End
system. Base address
Point
Point
Point
registers are used to
Figure 3. Non-Transparent Port
translate addresses;
doorbell registers are used to send interrupts between the
address domains; and scratchpad registers (accessible by
both CPUs) allow inter-processor communication (see
Figure 3).
SerDes Power and Signal Management
The PEX 8724 provides low power capability that is fully
compliant with the PCIe power management specification
and supports software control of the SerDes outputs to
allow optimization of power and signal strength in a
system. Furthermore, the SerDes block supports
loop-back
modes
and
advanced reporting of error conditions,
which enables efficient management of the entire system.
Interoperability
The PEX 8724 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
© PLX Technology, www.plxtech.com
Page 2 of 5
10/7/2010, Version 1.0