PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-38. 14Ch Port VC Capability 1 (All Ports)
Serial
Default
Bit(s)
Description
Type
EEPROM
Extended VC Count
0
RO
Yes
1
0 = PEX 8532 supports only the default Virtual Channel (VC0)
1 = PEX 8532 ports support one extended Virtual Channel (VC1)
3:1
Reserved
000b
Low-Priority Extended VC Count
For Strict Priority arbitration, this bit indicates the number of extended Virtual
Channels (those in addition to the default Virtual Channel 0) that belong to the
Low-Priority Virtual Channel group for this PEX 8532 port.
PEX 8532 Serial EEPROM register initialization capability is used to change
this field to 1 to also set VC1 to the Low-Priority Virtual Channel group.
4
RO
Yes
0
0 = For this PEX 8532 port, only the default Virtual Channel 0 belongs
to the Low-Priority Virtual Channel group
1 = For this PEX 8532 port, VC0 and VC1 belong to the Low-priority
Virtual Channel group
7:5
9:8
Reserved
000b
00b
Reference Clock
Not supported
Cleared to 00b.
RO
RO
No
No
Port Arbitration Table Entry Size
Not supported
11:10
00b
Cleared to 00b.
31:12 Reserved
0-0h
Register 11-39. 150h Port VC Capability 2 (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
VC Arbitration Capability
Bit 0 value of 1 indicates Round-Robin (Hardware-Fixed) Arbitration scheme
is supported.
Bit 1 value of 1 indicates Weighted Round-Robin Arbitration with 32 phases
is supported.
1:0
RO
Yes
Yes
11b
23:2
Reserved
0-0h
07h
VC Arbitration Table Offset
Virtual Channel Arbitration Table zero-based offset in Quad DWords (16 bytes)
from the base address of PEX 8532 port Virtual Channel Capability structure.
31:24
RO
194
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
