February, 2007
Power Budgeting Extended Capability Registers
11.11
Power Budgeting Extended Capability Registers
This section details the PEX 8532 Power Budgeting Extended Capability registers. The register map is
defined in Table 11-9.
Table 11-9. PEX 8532 Power Budgeting Extended Capability Register Map (All Ports)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Extended Capability ID (0004h)
Data Select
Capability
Next Capability Offset (148h)
Version (1h)
138h
Reserved
13Ch
140h
144h
Power Budgeting Data
Reserved
Power Budget Capability
Register 11-33. 138h Power Budgeting Extended Capability (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Extended Capability ID
15:0
RO
Yes
Yes
0004h
Set to 0004h, as required by the PCI Express Base r1.0a.
Capability Version
19:16
31:20
RO
RO
1h
Set to 1h, as required by the PCI Express Base r1.0a.
Next Capability Offset
Yes
148h
Set to 148h, which addresses the PEX 8532 Virtual Channel Extended Capability
registers.
Register 11-34. 13Ch Data Select (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Data Select
Indexes the Power Budgeting Data reported by way of eight Power Budgeting Data
registers per port and selects the DWord of Power Budgeting Data that appears in
each Power Budgeting Data register. Index values start at 0, to select the first
DWord of Power Budgeting Data; subsequent DWords of Power Budgeting Data
are selected by increasing index values 1 to 7.
7:0
RW
Yes
00h
31:8
Reserved
0-0h
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
191
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