Oxford Semiconductor, Inc.
OXU200 Data Sheet
Table 8 OXU200
100-Pin LQFP
Pin Allocations (Sheet 2 of 2)
Pin
No.
Bits
1
I
Type
(1)
Name
Description
Clock Interface (2 pins)
50
OSC
1
Input. A 12 MHz passive crystal should be connected
across the two pins (OSC
1
and OSC
2
). Optionally, a
12 MHz oscillator can be connected to OSC
1
while
keeping OSC
2
unconnected
Output
Internal voltage regulator output of 1.8 V. This output
must be connected to the V
DD1.8
supply of the chip
(and may be connected to V
DDW
if wide-range IO is at
1.8 V)
Factory test mode. This pin should be grounded or
left floating (has an internal pull-down) for normal
operation. Pull-down is always enabled
This pin must be grounded for normal operation
Reserved. These pins must be grounded
No connection. These pins should be left floating
49
80
1
1
O
O
OSC
2
V
REGOUT
Internal Voltage Regulator (1 pin)
Test (2 pins)
87
1
ID
TEST
64
91, 94, 93
34, 36, 37, 38, 52,
54, 55, 58, 59, 60,
61, 62, 63, 67, 68,
71, 76, 77, 79, 92
Note to Table 8:
1
3
20
I
-
-
XMODE
RSVD
0
, RSVD
1
, RSVD
2
NC
Miscellaneous (23 pins)
1
Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply:
L—Logic Level
M
(2)
Multi-voltage:
3.3 V CMOS
2.5 V CMOS
1.8 V CMOS
Schmitt Trigger
W—Tolerance
5
5V
3.3 V
I
O
B
2
3
X—Type
Input
Output
Bidirectional
U
D
Y—Pull
Pull up
Pull down
None
Z—Drive
C
(3)
T—Tristate
T
Tristate
Normal
S
Program to 3.3, 2.5, or 1.8 V by setting the V
IO
voltage level.
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐
tion Register (0x034).
DS-0051
Mar 07
External—Free Release
9
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