PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
CONDITIONS
MIN.
TYP.
MAX.
UNITS
With capacitive decoupling between
VDD and GND.
2.5
ps
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
36MHz @100Hz offset
36MHz @1kHz offset
36MHz @10kHz offset
36MHz @100kHz offset
36MHz @1MHz offset
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-110
-130
-138
-145
5. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage at
CMOS level
FXIN = 36MHz
Output load of 15pF
IDD
VDD
VOLC
5
6
mA
V
2.25
3.63
0.4
IOL = +4mA
V
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
VOHC
IOH = -4mA
VDD – 0.4
8
V
For VOL<0.4V or VOH>2.4V
9.5
mA
mA
V
±50
VCON
0
VDD
6. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
17
36
MHz
pF
µW
µW
pF
-
Crystal Loading Rating (VCON = 1.65V)
CL (xtal)
8.5
50
Maximum Sustainable Drive Level
200
Operating Drive Level
C0
5
C0/C1
ESR
250
30
RS
Ω
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/08/06 Page 4
PLL [ PHASELINK CORPORATION ]
