PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT
DIE SPECIFICATIONS
32 mil
(812,986)
8
Name
Value
XOUT
1
2
XIN
Size
39 x 32 mil
GND
OE^
7
Reverse side
Pad dimensions
Thickness
VDD
80 micron x 80 micron
10 mil
VDD
CLK
6
5
VCON
GND
3
4
DIE ID: PLL500-17: C500A0404-04A
(0,0)
Y
X
Note: ^ denotes internal pull up
PACKAGE PIN and DIE PAD ASSIGNMENT
Pin#
Die Pad Position
Name
Type
Description
SOP-8 SOT23-6
X (µm)
94.183
94.157
Y (µm)
768.599
605.029
XIN
1
2
6
5
I
Crystal input pin.
VDD power supply pin. Only one VDD pin is nec-
essary.
VDD
P
VCON
GND
CLK
3
4
5
4
2
3
94.183
94.193
715.472
331.756
140.379
203.866
I
Frequency control voltage input pin.
Ground pin.
P
O
Output clock pin.
VDD power supply pin. Only one VDD pin is nec-
essary.
VDD
OE
6
7
8
-
-
715.307
715.472
476.906
455.726
626.716
888.881
P
I
Output Enable input pin. Disables the output when
low. Internal pull-up enables output by default if
pin is not connected to low.
XOUT
1
I
Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/08/06 Page 2
PLL [ PHASELINK CORPORATION ]
