PixArt Imaging Inc.
PAS109B
CMOS Image Sensor IC
SDA
SCL
DATA
CHANGE
ALLOWED
DATA
STABLE
Fig 5.2 Valid Data
5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)
ꢀ S : Start
ꢀ A : Acknowledge by slave
ꢀ P : Stop
ꢀ RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle.
RW=1 read cycle, RW=0 write cycle.
ꢀ SUBADDRESS : The address values of PAS109B internal control registers
(Please refer to PAS109B register description)
1ST BYTE
2ND BYTE
n BYTEs + A
S
SLAVE ID (7 BIT)
RW
A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS109B) issues acknowledgment,
the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS109B acknowledgment, the
master places the 8 bits data on SDA line and transmit to PAS109B control register (address was assigned by
2nd byte). After PAS109B issue acknowledgment, the master can generate a stop condition to end of this write
cycle. In the condition of multi-byte write, the PAS109B sub-address is automatically increment after each
DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value
inside PAS109B can be programming via this way. (Please refer to Fig 5.3.)
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7
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
V1.1, Mar. 2002
PIXART [ PIXART IMAGING INC. ]
