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ADNS-7550 参数 Datasheet PDF下载

ADNS-7550图片预览
型号: ADNS-7550
PDF下载: 下载PDF文件 查看货源
内容描述: 集成模制引线框架的DIP传感器 [Integrated molded lead-frame DIP Sensor]
分类和应用: 传感器光电二极管
文件页数/大小: 32 页 / 822 K
品牌: PIXART [ PIXART IMAGING INC. ]
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PixArt Imaging Inc.  
ADNS-7550 Integrated Molded Lead-Frame DIP Sensor  
AC Electrical Specifications  
Electrical Characteristics over recommended operating conditions. (Typical values at 25 °C, VDD=5.0V, VDDIO= 2.8V)  
Parameter  
Symbol  
Minimum Typical Maximum Units Notes  
Motion delay  
after reset  
tMOT-RST  
23  
ms  
From SW_RESET register write to valid motion,  
assuming motion is present  
Shutdown  
tSTDWN  
50  
ms  
ms  
From Shutdown mode active to low current  
Wake from  
shutdown  
tWAKEUP  
23  
From Shutdown mode inactive to valid motion.  
Notes: A RESET must be asserted after a shutdown.  
Refer to section “Notes on Shutdown also note  
tMOT-RST  
MISO rise time  
MISO fall time  
tr-MISO  
150  
150  
300  
300  
120  
ns  
ns  
ns  
CL = 100pF  
CL = 100pF  
tf-MISO  
MISO delay  
after SCLK  
tDLY-MISO  
From SCLK falling edge to MISO data valid, no load  
conditions  
MISO hold time  
MOSI hold time  
MOSI setup time  
thold-MISO 0.5  
thold-MOSI 200  
tsetup-MOSI 120  
1/fSCLK  
us  
ns  
ns  
μs  
Data held until next falling SCLK edge  
Amount of time data is valid after SCLK rising edge  
From data valid to SCLK rising edge  
SPI time between  
write commands  
tSWW  
30  
From rising SCLK for last bit of the first data byte, to  
rising SCLK for last bit of the second data byte.  
SPI time between  
write and read  
commands  
tSWR  
20  
μs  
ns  
From rising SCLK for last bit of the first data byte, to  
rising SCLK for last bit of the second address byte.  
SPI time between  
read and subsequent  
commands  
tSRW  
tSRR  
500  
From rising SCLK for last bit of the first data byte, to  
falling SCLK for the first bit of the address byte of  
the next command.  
SPI read address  
-data delay  
tSRAD  
tBEXIT  
4
μs  
ns  
From rising SCLK for last bit of the address byte, to  
falling SCLK for first bit of data being read.  
NCS inactive after  
motion burst  
500  
Minimum NCS inactive time after motion burst  
before next SPI usage  
NCS to SCLK active  
tNCS-SCLK  
tSCLK-NCS  
120  
120  
ns  
ns  
From NCS falling edge to first SCLK rising edge  
SCLK to NCS inactive  
(for read operation)  
From last SCLK rising edge to NCS rising edge, for  
valid MISO data transfer  
SCLK to NCS inactive  
(for write operation)  
tSCLK-NCS  
20  
us  
From last SCLK rising edge to NCS rising edge, for  
valid MOSI data transfer  
NCS to MISO high-Z  
MOTION rise time  
MOTION fall time  
tNCS-MISO  
tr-MOTION  
tf-MOTION  
IDDT  
500  
300  
300  
45  
ns  
From NCS rising edge to MISO high-Z state  
150  
150  
ns  
CL = 100pF  
CL = 100pF  
ns  
Transient Supply  
Current  
mA  
Max supply current during a VDD ramp from 0 to  
2.8V  
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.  
PixArt Imaging Inc.  
E-mail: fae_service@pixart.com.tw  
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