Philips Semiconductors
Product specification
Octuple 6-bit DACs with
I
2
C-bus
TDA8444; TDA8444T;
TDA8444AT
connected between these pins and V
EE
. This means that
normal bus line voltage should not exceed 5.5 V.
The address inputs A0, A1 and A2 can be easily
programmed by either a connection to V
EE
(An = 0) or V
CC
(An = 1). If the inputs are left floating the result will be
An = 1.
V
MAX
The V
MAX
input gives a means of compressing the DAC
output voltage swing. The maximum DAC output voltage
will be equal to V
MAX
+ V
DAC(min)
, while the 6-bit resolution
is maintained. This enables a higher voltage resolution for
smaller output swings.
DACs
The DACs consist of a 6-bit data-latch, current switches
and an opamp. The current sources connected to the
switches have values with weights 2
0
to 2
5
. The sum of the
switched on currents is converted by the opamp into a
voltage between approximately 0.5 and 10.5 V if
V
MAX
= V
CC
= 12 V. The DAC outputs are short-circuit
protected against V
CC
and V
EE
. Capacitive load on the
DAC outputs should not exceed 2 nF in order to prevent
possible oscillations at certain levels. The temperature
coefficient for each of the outputs remains in all possible
conditions well below 0.1 LSB per Kelvin.
The circuit will not react to other combinations of the
4 instruction bits I3 to I0 than 0 or F, but will still generate
an acknowledge. The difference between
instruction 0 and F is only important when more than one
data byte is sent within one transmission. Instruction 0
causes the data bytes to be written into the DAC-latches
with consecutive subaddresses starting with the
subaddress given in the instruction byte (auto-increment of
subaddress), while instruction F will cause a consecutive
writing of the data bytes into the same DAC-latch whose
subaddress was given in the instruction byte. In case of
only one data byte the DAC-latch with the subaddress
equal to the subaddress in the instruction byte will receive
the data.
Valid subaddresses are: 0H to 7H.
The subaddresses correspond to DAC0 to DAC7.
The Auto-Increment (AI) function of instruction 0,
however, works on all possible subaddresses 0 to F in
such a way that next to subaddress F, subaddress 0 will
follow, and so on.
The data will be latched into the DAC-latch on the
positive-going edge of the acknowledge related clock
pulse.
The specification of the SCL and SDA I/O meets the
I
2
C-bus specification. For protection against positive
voltage pulses on pins 3 and 4, zener diodes are
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
CC
I
CC
P
(max)
V
i(n)
supply voltage
supply current
maximum power dissipation
input voltage
pins SDA and SCL
pins V
MAX
, A0 to A2 and DAC0 to DAC7
I
n
T
stg
T
amb
current in all pins except V
CC
and V
EE
storage temperature
operating ambient temperature
PARAMETER
−0.5
−10
−
−0.5
−0.5
−0.5
−
−65
−20
MIN.
+18
+40
500
+5.9
+5.9
V
CC
+ 0.5
±10
+150
+70
MAX.
V
mA
mW
V
V
V
mA
°C
°C
UNIT
QUALITY SPECIFICATION
In accordance with
“SNW-FQ-611-E”.
1999 Apr 29
6
PHILIPS [ NXP SEMICONDUCTORS ]
