Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4856
PLL2 soft start sequence and PLL2 soft-down sequence
MGS279
handbook, full pagewidth
V
HPLL2
4.6 V continuous blanking off
PLL2 enabled
frequency detector enabled
HDRV/HFLB protection enabled
4.0 V BDRV duty cycle has reached nominal value
3.2 V BDRV duty cycle begins to increase
HDRV duty cycle has reached nominal value
1.8 V
HDRV duty cycle begins to increase
time
a. PLL2 soft start sequence, if VCC > 8.6 V.
MGS280
handbook, full pagewidth
V
HPLL2
4.6 V continuous blanking activated on pins CLBL and HUNLOCK
PLL2 disabled
frequency detector disabled
HDRV/HFLB protection disabled
(1)
4.0 V BDRV duty cycle begins to decrease
2.8 V BDRV floating
(1)
HDRV duty cycle begins to decrease
1.8 V HDRV floating
time
b. PLL2 soft-down sequence, if VCC > 8.6 V.
(1) HDRV and BDRV are floating for VCC < 8.6 V.
Fig.25 Activation of PLL2 soft-start sequence and PLL2 soft-down sequence via the I2C-bus.
1999 Jul 13
43
NXP [ NXP ]
