Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADJUSTMENT OF VERTICAL POSITION; see Figs 3 to 7
VOFFS
vertical position (referenced to register VOFFS = 0
−
−
−
−
−
−
−4
−
%
100% vertical size)
register VOFFS = 15
4
−
−
−
−
−
%
%
%
%
%
register VOFFS = 8
0.25
−11.5
11.5
0.09
VPOS
vertical position (referenced to register VPOS = 0
100% vertical size)
register VPOS = 127
register VPOS = 64
ADJUSTMENT OF VERTICAL LINEARITY; see Figs 6 and 27
VLIN
vertical linearity (S-correction) register VLIN = 0; control
−
−
−
−
2
−
%
%
%
%
bit VSC = 0; note 8
register VLIN = 15; control
bit VSC = 0; note 8
46
0
−
register VLIN = X; control
bit VSC = 1; note 8
−
δVLIN
symmetry error of S-correction maximum VLIN
−
±0.7
ADJUSTMENT OF VERTICAL LINEARITY BALANCE; see Fig.7
VLINBAL
vertical linearity balance
(referenced to 100% vertical
size)
register VLINBAL = 0;
note 8
−1.85
−1.40
1.40
0.08
0
−0.95
%
%
%
%
%
%
register VLINBAL = 15;
note 8
0.95
1.85
register VLINBAL = 8;
note 8
−
−
−
−
−
−
−
−
VMOIRE
modulation of vertical picture
position by 1⁄2 vertical
frequency (related to 100%
vertical size)
register VMOIRE = 0;
control bit MOD = 0
register VMOIRE = 63;
control bit MOD = 0
0.03
0
moire cancellation off
control bit MOD = 1
Vertical output stage: pin VOUT1 and VOUT2; see Fig.27
∆IVOUT(nom)(p-p)
nominal differential output
current (peak-to-peak value)
∆IVOUT = IVOUT1 − IVOUT2
nominal settings; note 8
;
0.76
0.54
0.85
0.6
0.94
0.66
mA
mA
Io(VOUT)(max)
maximum output current at
pins VOUT1 and VOUT2
control bit VOVSCN = 1
VVOUT
allowed voltage at outputs
0
−
−
4.2
V
E(offset)(max)(V)
maximum offset error of vertical nominal settings; note 8
output currents
−
±2.5
%
LEV(max)
maximum linearity error of
vertical output currents
nominal settings; note 8
−
−
±1.5
%
1999 Oct 25
21
NXP [ NXP ]
