Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
PINNING
SYMBOL
V
SSD1
DP4
DP5
DP6
DP7
RCV1
RCV2
V
SSD2
VP0
VP1
VP2
VP3
VP4
VP5
VP6
VP7
V
DDD1
SEL_ED
V
SSD3
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
SSD4
RCM1
RCM2
KEY
OSD0
OSD1
OSD2
V
SSD5
CDIR
V
DDD2
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
digital ground 5
On-Screen Display data. This is the index for the internal OSD look-up table.
digital ground 4
Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal.
MPEG Port. It is an input for CCIR 656 style multiplexed YUV data.
digital supply voltage 1
digital ground 1
DESCRIPTION
SAA7185
Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
MPU interface. If it is LOW, they are the UV lines of the Video Port.
Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides an HS/HREF/CBL signal.
digital ground 2
Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit
DIG-TV2 format is used, this is the Y data.
Select Encoder Data. Selects data either from MPEG port or from video port as encoder input.
digital ground 3
Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder.
Key signal for OSD. It is active HIGH.
Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC
and CREF are generated by the internal crystal oscillator.
digital supply voltage 2
1996 Jul 08
4
PHILIPS [ NXP SEMICONDUCTORS ]
