Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.9
High Performance Scaler (HPS)
7.9.2
SCALING UNIT
Depending on the selected port modes the incoming and
scaled data are formatted/reformatted (8-bit or 16-bit), and
the corresponding reference signals are generated. Based
on these reference signals the active processing window is
defined in a versatile way via programming.
The scaling to a randomly sized window is performed in
three steps:
• Horizontal prescaling (bandwidth limitation for
anti-aliasing, via FIR prefiltering and subsampling)
• Vertical scaling (generating phase interpolated or
The programming register can be loaded during the
processing of the previous field, frame or line by RPS.
In this way each D1 port gets processed in a field or frame
alternating manner. If the incoming signals are not locked,
then the acquisition is waiting for the new active video of
the subsequent field. The corresponding fields are
detected by a ‘Field Detection’. To support asynchronous
video processing in the two video paths, each D1 port has
its own ‘Field Detection’. The video signal source is also
source for the qualify signal PXQ.
vertically low-passed lines)
• Horizontal phase scaling (phase correct scaling to the
new geometric relations).
The scaling process generates a new pixel/clock qualifier
sequence. There are restrictions in the combination of
input sample rate and up or downscaling mode and scaling
factor. The maximum resulting output sample rate at the
DD1 port is 1⁄2LLC, because of compliance to the
CCIR 656 format.
Before being processed in the central scaling unit the
incoming data passes to the BCS control unit, where
monitor control functions for adjusting Brightness and
Contrast (luminance) as well as Saturation (chrominance)
are implemented (BCS control). The horizontal scaling is
carried out in two steps; a prefiltering (bandwidth limitation
for initialising) and a horizontal fine scaling. Between them
the vertical processing is performed.
7.9.2.1
Horizontal prescaling
The incoming pixels in the selected range are
pre-processed in the horizontal prescaler (first stage of the
scaling unit). It consists of a FIR prefilter and a pixel
collecting subsampler.
7.9.2.2
FIR prefilter
The video components Y, U and V are FIR pre-filtered to
reduce the signal bandwidth according to the downscale
for factors between 1 and 1⁄2, so that aliasing, due to signal
bandwidth expansion, is reduced. The prefilter consists of
3 filter stages. The transfer functions are listed in the
Section 7.12. The prefilter is controlled by the ‘Scaler
Register’ bits PFY3 to PFY0 and PFUV3 to PFUV0 in the
HPS horizontal prescale register (see Table 79).
7.9.1
BCS CONTROL
The parameters for brightness, contrast and saturation
can be adjusted in the BCS control unit. The luminance
signal can be controlled by the bits BRIG7 to BRIG0 and
CONT6 to CONT0. The chrominance signal can be
controlled by the bits SAT6 to SAT0.
Brightness control (BRIG7 to BRIG0):
• 00H; minimum offset
Figures 19 and 20 show frequency response
characteristics and the corresponding scaler register
settings. The prefilter operates on YUV 4 : 4 : 4 data.
As U and V are generated by simple chroma pixel
doubling, the UV prefilter should also be used to generate
the interpolated chroma values.
• 80H; CCIR level
• FFH; maximum offset.
Contrast control (CONT6 to CONT0):
• 00H; luminance off
• 40H; CCIR level
7.9.2.3
Subsampler
• 7FH; 1.9999 amplitude.
To improve the scaling performance for scales less than
1⁄2 down to icon size, a FIR filtering subsampler is
available. It performs a subsampling of the incoming data
by a factor of 1/N, where N = 1 to 64. This operation is
controlled by XPSC, where N = XPSC + 1. Where
NIP = number of input pixels/line and NOP = number of
desired output pixels/line, the basic equation to calculate
XPSC is:
Saturation control (SAT6 to SAT0):
• 00H; colour off
• 40H; CCIR level
• 7FH; 1.9999 amplitude.
Limits: All resulting output values are limited to minimum
(equals 0) and maximum (equals 255).
XPSC = TRUNC [(NIP/NOP) − 1]
1998 Apr 09
69
NXP [ NXP ]
