Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
15.2.19 SUBADDRESS 12H
Table 55 RT signal control: RTS0 output; 12H[3:0]
The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].
RTS0 OUTPUT
RTSE03 RTSE02 RTSE01 RTSE00
3-state
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Constant LOW
CREF (13.5 MHz toggling pulse; see Fig.23)
CREF2 (6.75 MHz toggling pulse; see Fig.23)
HL; horizontal lock indicator (note 1):
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
VL = 0: unlocked
0
0
1
1
0
1
1
0
VL = 1: locked
DL, vertical and horizontal lock and colour detected:
DL = 0: unlocked
DL = 1: locked
Reserved
0
1
1
0
1
0
1
0
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.23).
HS:
1
0
0
1
programmable width in LLC8 steps via HSB[7:0]06H[7:0] and
HSS[7:0]07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]
(see Fig.23)
HQ; HREF gated with VGATE
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
Reserved
V123; vertical sync (see vertical timing diagrams Figs 21 and 22)
VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],
VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]
LSBs of the 9-bit ADC’s
1
1
1
1
1
1
0
1
FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing
diagrams Figs 21 and 22
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
2000 Mar 15
99
NXP [ NXP ]
