Philips Semiconductors
Product specification
9-bit video input processor
7
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12 to 15
I/O/P
I
P
P
I
I
P
I
I
O
P
P
O
analog input 22
ground for analog supply voltage channel 1
positive supply voltage for analog channel 1 (+3.3 V)
analog input 11
DESCRIPTION
SAA7113H
SYMBOL
AI22
V
SSA1
V
DDA1
AI11
AI1D
AGND
AI12
TRST
AOUT
V
DDA0
V
SSA0
VPO7 to
VPO4
differential analog input for AI11 and AI12; has to be connected to ground via a
capacitor; see application diagram of Fig.31
analog signal ground connection
analog input 12
test reset input (active LOW), for boundary scan test; notes 1, 2 and 3
analog test output; for testing the analog input channels, 75
Ω
termination possible
positive supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)
ground for internal clock generation circuit
digital VPO-bus output signal; higher bits of the 8-bit output bus. The output data
types of the VPO-bus are controlled via I
2
C-bus registers LCR2 to LCR24;
see Table 4. If I
2
C-bus bit VIPB = 1, the higher bits of the digitized input signal are
connected to these outputs, configured by the I
2
C-bus control signals
MODE3 to MODE0
ground 1 or digital supply voltage input E (external pad supply)
line-locked system clock output (27 MHz)
digital supply voltage E1 (external pad supply 1; +3.3 V)
digital VPO-bus output signal; lower bits of the 8-bit output bus. The output data types
of the VPO-bus are controlled via I
2
C-bus registers LCR2 to LCR24; see Table 4.
If I
2
C-bus bit VIPB = 1, the lower bits of the digitized input signal are connected to
these outputs, configured by the I
2
C-bus control signals MODE3 to MODE0
serial data input/output (I
2
C-bus) 5 V-compatible
serial clock input (I
2
C-bus) 5 V-compatible
real-time control output: contains information about actual system clock frequency,
field rate, odd/even sequence, decoder status, subcarrier frequency and phase and
PAL sequence (see external document
“RTC Functional Description”,
available on
request); the RTCO pin is enabled via I
2
C-bus bit OERT;
this pin is also used as an
input pin for test purposes and has an internal pull-down resistor; do not
connect any pull-up resistor to this pin
real-time signal output 0: multi functional output, controlled by I
2
C-bus bits
RTSE03 to RTSE00; see Table 49. RTS0 is strapped during power-on or CE driven
reset, defines which I
2
C-bus slave address is used; 0 = 48H for write, 49H for read,
external pull-down resistor of 3.3 kΩ is needed; 1 = 4AH for write, 4BH for read,
default slave address (default, internal pull-up)
real-time signal I/O terminal 1: multi functional output, controlled by I
2
C-bus bit
RTSE13 to RTSE10; see Table 50
ground for internal digital core supply
internal core supply (+3.3 V)
digital ground for internal crystal oscillator
second terminal of crystal oscillator; not connected if external clock signal is used
V
SSDE1
LLC
V
DDDE1
VPO3 to
VPO0
16
17
18
19 to 22
P
O
P
O
SDA
SCL
RTCO
23
24
25
I/O
I
(I/)O
RTS0
26
(I/)O
RTS1
V
SSDI
V
DDDI
V
SSDA
XTAL
27
28
29
30
31
I/O
P
P
P
O
1999 Jul 01
6
PHILIPS [ NXP SEMICONDUCTORS ]
