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SAA7113H 参数 Datasheet PDF下载

SAA7113H图片预览
型号: SAA7113H
PDF下载: 下载PDF文件 查看货源
内容描述: 9位视频输入处理器 [9-bit video input processor]
分类和应用: 消费电路商用集成电路
文件页数/大小: 80 页 / 281 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product specification
9-bit video input processor
1
FEATURES
SAA7113H
Four analog inputs, internal analog source selectors,
e.g. 4
×
CVBS or 2
×
Y/C or (1
×
Y/C and 2
×
CVBS)
Two analog preprocessing channels in differential
CMOS style for best S/N-performance
Fully programmable static gain or automatic gain control
for the selected CVBS or Y/C channel
Switchable white peak control
Two built-in analog anti-aliasing filters
Two 9-bit video CMOS Analog-to-Digital Converters
(ADCs), digitized CVBS or Y/C-signals are available on
the VPO-port via I
2
C-bus control
On-chip clock generator
Line-locked system clock frequencies
Digital PLL for horizontal sync processing and clock
generation, horizontal and vertical sync detection
Requires only one crystal (24.576 MHz) for all standards
Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
Luminance and chrominance signal processing for
PAL BGHI, PAL N, combination PAL N, PAL M,
NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and
SECAM
User programmable luminance peaking or aperture
correction
Cross-colour reduction for NTSC by chrominance comb
filtering
PAL delay line for correcting PAL phase errors
Brightness Contrast Saturation (BCS) and hue control
on-chip
Real-time status information output (RTCO)
Two multi functional real-time output pins controlled by
I
2
C-bus
Multi-standard VBI-data slicer decoding World Standard
Teletext (WST), North-American Broadcast Text
System (NABTS), closed caption, Wide Screen
Signalling (WSS), Video Programming System (VPS),
Vertical Interval Time Code (VITC) variants
(EBU/SMPTE) etc.
Standard ITU 656 YUV 4 : 2 : 2 format (8-bit) on VPO
output bus
Enhanced ITU 656 output format on VPO output bus
containing:
– active video
– raw CVBS data for INTERCAST applications
(27 MHz data rate)
– decoded VBI data
Boundary scan test circuit complies with the
“IEEE Std.
1149.b1 - 1994”
(ID-Code = 1 7113 02B)
I
2
C-bus controlled (full read-back ability by an external
controller, bit rate up to 400 kbits/s)
Low power (<0.5 W), low voltage (3.3 V), small package
(QFP44)
Power saving mode by chip enable input
5 V tolerant digital I/O ports
Detection of copy protected input signals according to
the macrovision standard. Can be used to prevent
unauthorized recording of pay-TV or video tape signals.
2
APPLICATIONS
Notebook (low power consumption)
PCMCIA card application
AGP based graphics cards
Image processing
Video phone applications
Intercast and PC teletext applications
Security applications.
1999 Jul 01
3