Philips Semiconductors
SAA7113H
9-bit video input processor
Pin description
…continued
Pin
Type
Description
digital VPO-bus output signal; higher bits of the 8-bit output bus. The
output data types of the VPO-bus are controlled via I
2
C-bus registers
LCR2 to LCR24 (see
If I
2
C-bus bit VIPB = 1, the higher bits
of the digitized input signal are connected to these outputs,
configured by the I
2
C-bus control signals MODE3 to MODE0.
ground 1 or digital supply voltage input E (external pad supply)
line-locked system clock output (27 MHz)
digital supply voltage E1 (external pad supply 1; 3.3 V)
digital VPO-bus output signal; lower bits of the 8-bit output bus. The
output data types of the VPO-bus are controlled via I
2
C-bus registers
LCR2 to LCR24 (see
If I
2
C-bus bit VIPB = 1, the lower bits
of the digitized input signal are connected to these outputs,
configured by the I
2
C-bus control signals MODE3 to MODE0.
serial data input/output (I
2
C-bus)
serial clock input (I
2
C-bus) with inactive output path
real-time control output; contains information about actual system
clock frequency, field rate, odd/even sequence, decoder status,
subcarrier frequency and phase and PAL sequence (see external
document
“RTC Functional Description”,
available on request); the
RTCO pin is enabled via I
2
C-bus bit OERT.
Remark:
this pin is also used as an input pin for test purposes and
has an internal pull-down resistor; do not connect any pull-up resistor
to this pin
12 to 15 O
Table 3:
Symbol
VPO7 to
VPO4
V
SSDE1
LLC
V
DDDE1
VPO3 to
VPO0
16
17
18
P
O
P
19 to 22 O
SDA
SCL
RTCO
23
24
25
I/O
I(/O)
(I/)O
RTS0
26
(I/)O
real-time signal output 0: multifunctional output, controlled by I
2
C-bus
bits RTSE03 to RTSE00 (see
RTS0 is strapped during
power-on or CE driven reset, defines which I
2
C-bus slave address is
used; LOW = 48h for write, 49h for read, external pull-down resistor
of 3.3 kΩ is needed and HIGH = 4Ah for write, 4Bh for read, default
slave address (default, internal pull-up).
real-time signal I/O terminal 1: multifunctional output, controlled by
I
2
C-bus bit RTSE13 to RTSE10 (see
ground for internal digital core supply
internal core supply (3.3 V)
digital ground for internal crystal oscillator
second terminal of crystal oscillator; not connected if external clock
signal is used
input terminal for crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal
digital positive supply voltage for internal crystal oscillator (3.3 V)
digital supply voltage E2 (external pad supply 2; 3.3 V)
ground 2 for digital supply voltage input E (external pad supply)
test data output for boundary scan test; see
test clock input for boundary scan test; see
test data input for boundary scan test; see
test mode select input for boundary scan test or scan test; see
RTS1
V
SSDI
V
DDDI
V
SSDA
XTAL
XTALI
V
DDDA
V
DDDE2
V
SSDE2
TDO
TCK
TDI
TMS
27
28
29
30
31
32
33
34
35
36
37
38
39
I/O
P
P
P
O
I
P
P
P
O
I
I
I
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
6 of 75
PHILIPS [ NXP SEMICONDUCTORS ]
