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AD2BYP AD1BYP
LUM
CHR
SECAM
PROCESSING
sequential
UV signals
8
TRST
TCK
TDI
37
38
39
QUADRATURE
DEMODULATOR
LEVEL
TEST
CONTROL
BLOCK
LOW-PASS
ADJUSTMENT,
BRIGHTNESS,
CONTRAST
AND
SATURATION
CONTROL
CHBW0
CHBW1
12, 13, 14,
TMS
15, 19, 20,
21, 22
36
TDO
VPO7
to
VPO0
Y
OUTPUT
FORMATTER
AND
PHASE
DEMODULATOR
SUBCARRIER
GENERATION
RESET
SUBCARRIER
INCREMENT
GENERATION
AND
UV
AMPLITUDE
DETECTOR
INTERFACE
GAIN
CONTROL
18
29
33
34
V
DDDE1
BURST GATE
ACCUMULATOR
HUEC
DIVIDER
COMB
FILTERS
SECAM
V
DDDI
AND Y-DELAY
COMPENSATION
UV
POWER-ON
CONTROL
V
LOOP FILTER
DDDA
RECOMBINATION
V
DDDE2
CODE
CSTD[2:0]
INCS
FCTC
BRIG
CONT
SATN
DCCF
OFTS0
OFTS1
OEYC
OEHV
VRLN
GPSW[1:0]
RTSE1[3:0]
RTSE0[3:0]
VIPB
CE CLOCKS
16
28
30
35
V
SSDE1
f
/2 switch signal
H
V
SSDI
COLO
VBI DATA BYPASS
UPSAMPLING
FILTER
VSTA[8:0]
VSTO[8:0]
V
SSDA
V
SSDE2
25
RTCO
MULTISTANDARD DATA SLICER
INTERFACING
DATA SLICER
INPUT
MULTISTANDARD DATA SLICER
mhb328
Y
LUM
Fig 10. Chrominance circuit, text slicer, VBI-bypass, output formatting, power and test control
NXP [ NXP ]
