SAA7113H
Philips Semiconductors
9-bit video input processor
ANALOG INPUT
ADC
1
0
NO BLANKING ACTIVE
VBLK
<- CLAMP
GAIN ->
1
1
0
0
HCL
HSY
0
1
1
0
1
0
< CLL
< SBOT
> WIPE
slow + GAIN
NO CLAMP
+ CLAMP
− CLAMP
fast − GAIN
+ GAIN
− GAIN
mgc647
WIPE = white peak level (254);
SBOT = sync bottom level (1);
CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse;
HCL = horizontal clamp pulse.
Fig 8. Clamp and gain flow
8.3 Chrominance processing
The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature
demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0°
and 90° phase relationship to the demodulator axis). The frequency is dependent on the
present color standard. The output signals of the multipliers are low-pass filtered (four
programmable characteristics) to achieve the desired bandwidth for the color difference
signals (PAL and NTSC) or the 0° and 90° FM signals (SECAM).
The color difference signals are fed to the Brightness/Contrast/Saturation block (BCS),
which includes the following five functions:
• Automatic Gain Control (AGC) for chrominance PAL and NTSC
• Chrominance amplitude matching (different gain factors for (R − Y) and (B − Y) to
achieve ITU-R BT 601 levels CR and CB for all standards)
• Chrominance saturation control
• Luminance contrast and brightness
• Limiting YUV to the values 1 (minimum) and 254 (maximum) to fulfil ITU-R BT 601
requirements.
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
11 of 75
NXP [ NXP ]
