Philips Semiconductors
Product specification
Low voltage mixer FM IF system with filter amplifier
and data switch
SA639
CIRCUIT DESCRIPTION
The SA639 is an IF signal processing system suitable for second IF
or single conversion systems with input frequency as high as 1GHz.
The bandwidth of the IF amplifier is about 40MHz, with 44dB(v) of
gain from a 50Ω source. The bandwidth of the limiter is about
28MHz with about 58dB(v) of gain from a 50Ω source. However, the
gain/bandwidth distribution is optimized for 9.8MHz, 330Ω source
applications. The overall system is well-suited to battery operation
as well as high performance and high quality products of all types,
such as digital cordless phones.
The input stage is a Gilbert cell mixer with oscillator. Typical mixer
characteristics include a noise figure of 11dB, conversion power gain
of 9.2dB, and input third-order intercept of -9.5dBm. The oscillator
will operate in excess of 1GHz in L/C tank configurations. Hartley or
Colpitts circuits can be used up to 100MHz for xtal configurations.
Butler oscillators are recommended for xtal configurations up to
150MHz.
The output of the mixer is internally loaded with a 330Ω resistor
permitting direct connection to a 330Ω ceramic filter. The input
resistance of the limiting IF amplifiers is also 330Ω. With most 330Ω
ceramic filters and many crystal filters, no impedance matching
network is necessary. To achieve optimum linearity of the log signal
strength indicator, there must be a 6dB(v) insertion loss between the
first and second IF stages. If the IF filter or interstage network does
not cause 6dB(v) insertion loss, a fixed or variable resistor can be
added between the first IF output (Pin 20) and the interstage
network.
The signal from the second limiting amplifier goes to a Gilbert cell
quadrature detector. One port of the Gilbert cell is internally driven
by the IF. The other output of the IF is AC-coupled to a tuned
quadrature network. This signal, which now has a 90
°
phase
relationship to the internal signal, drives the other port of the
multiplier cell.
Overall, the IF section has a gain of 90dB. For operation at
intermediate frequency at 9.8MHz. Special care must be given to
layout, termination, and interstage loss to avoid instability.
The demodulated output (DATA) of the quadrature is a low
impedance voltage output. This output is designed to handle a
minimum bandwidth of 1MHz. This is designed to demodulate
wideband data, such as in DECT applications.
frequency response influence on the filter group delay characteristic
at a minimum. At the center of the carrier it is mandatory to provide
a filter output DC bias voltage of 1.6V in order to be within the input
common mode range of the external data comparator. The filter
output DC bias voltage specification holds for an exactly center
tuned demodulator tank and for the demodulator output connected
to the filter amplifier input.
Data Switch
The SA639 incorporates an active data switch used to derive the
data comparator reference voltage by means of an external
integration circuit. The data switch is typically closed for 10µs
before and during reception of the synchronization word pattern, and
is otherwise open. The external integration circuit is formed by an
R/C low pass with a time constant of 5 to 10µs.
The active data switch provides excellent tracking behavior over a
DC input range of 1.2 to 2.0V. For this range with an RC load (no
static current drawn), the DC output voltage will not differ more than
±5mV
from the input voltage. Since the active data switch is
designed to behave like a non-linear charge pump (to allow fast
tracking of the input signal without slew rate limitations under
dynamic conditions of a 576kHz input signal with 400mV
P-P
and the
RC load), the output signal will have a 340mV
P-P
output with a DC
average that will not vary from the input DC average by more than
±10mV.
The data switch is able to sink/source 3mA from/to the external
integration circuit in order to minimize the settling time after long
power-down periods (DECT paging mode). In addition, during
power-down conditions a reference voltage of approximately 1.6V
will be used as the input to the switch. The switch will be in a low
current mode to maintain the voltage on the external RC load. This
will further reduce the settling time of the capacitor after power-up.
It should be noted that during power-down the switch can only
source and sink a trickle current (10µA). Thus, the user should
make sure that other circuits (like the data comparator inputs) are
not drawing current from the RC circuit.
The data switch provides a slew rate better than 1V/µs in order to
track with system DC offset from receive slot to receive slot (DECT
idle lock or active mode). When the data switch is opened the
output is in a tri-state mode with a leakage current of less than
100nA. This reduces discharge of the external integration circuit.
When powered-down, the data switch will output a reference of
approximately 1.6V to maintain a charge on the external RC circuit.
A Receive Signal Strength Indicator (RSSI) completes the circuitry.
The output range is greater than 80dB and is temperature
compensated. This log signal strength indicator exceeds the criteria
for DECT cordless telephone. This signal drives an internal op amp.
The op amp is capable of rail-to-rail output. It can be used for gain,
filtering, or 2nd-order temperature compensation of the RSSI, if
needed.
NOTE: dB(v) = 20log V
OUT
/V
IN
Post Detection Filter Amplifier
The filter amplifier may be used to realize a group delay optimized
low pass filter for post detection. The filter amplifier can be
configured for Sallen & Key low pass with Bessel characteristic and
a 3dB cut frequency of about 800kHz.
The filter amplifier provides a gain of 0dB. The output impedance is
less than 500Ω in order to reduce frequency response changes as a
result of amplifier load variations. The filter amplifier has a 3dB
bandwidth of at least 4 MHz in order to keep the amplifier’s
1998 Feb 10
6
PHILIPS [ NXP SEMICONDUCTORS ]
