NXP Semiconductors
PHC2300
Complementary enhancement mode MOS transistors
4. Limiting values
Table 4.
Symbol
V
DS
V
GS
I
D
I
DM
P
tot
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
T
sp
= 80 °C; N-channel
T
sp
= 80 °C; P-channel
T
sp
= 25 °C; pulsed; N-channel
T
sp
= 25 °C; pulsed; P-channel
T
sp
= 80 °C
T
amb
= 25 °C
T
amb
= 25 °C
T
amb
= 25 °C
T
stg
T
j
[1]
[2]
[3]
[4]
[5]
[6]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
150 °C; N-channel
T
j
≥
25 °C; T
j
≤
150 °C; P-channel
Min
-
-
-20
-
-
-
-
-
-
-
-
-55
-55
Max
300
-300
20
340
-235
1.4
-0.9
1.6
1.8
0.9
1.2
150
150
Unit
V
V
V
mA
mA
A
A
W
W
W
W
°C
°C
storage temperature
junction temperature
Solder point temperature is the temperature at the soldering point of the drain leads.
Pulse width and duty cycle limited by maximum junction temperature.
Maximum permissible dissipation per MOS transistor (both devices may thus be loaded up to 1.6 W at the same time).
Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an R
th(a-tp)
(ambient to tie-point) of
27.5 K/W.
Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an R
th(a-tp)
(ambient to tie-point) of 90
K/W.
Maximum permissible dissipation if only one MOS transistor dissipates. Value based on a printed-circuit board with an R
th(a-tp)
(ambient
to tie-point) of 90 K/W.
2
P
tot
(W)
1.6
mda235
10
I
D
(A)
1
(1)
mda240
1.2
10
−
1
0.8
P
δ
=
t
p
T
10
−
2
0.4
t
p
t
T
DC
0
0
40
80
120
T
s
(°C)
160
10
−
3
1
10
10
2
V
DS
(V)
10
3
δ
= 0.01; T
sp
= 80 °C.
(1) R
DSon
limitation.
Fig 1.
PHC2300
Power derating curve
Fig 2.
SOAR; N-channel
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 05 — 24 February 2011
3 of 14
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